High performance designs often use the on-chip device PLLs for accurate test clock generation during testing. The on-chip clock generator is designed in a programmable way to facilitate the test generation process and it in turn creates additional constraints for the automatic test pattern generation (ATPG) tool. This paper describes an efficient and effective method to take the hardware restrictions originated from the on-chip clock generators into account in order to avoid generating clock sequences that cannot be produced by hardware. Experimental results on industrial designs show test pattern reduction and/or ATPG run time reduction when compared with the test generation method that enumerates valid clock sequences explicitly and restricts the test generation within enumerated test sequences.