IR-drop has become a major source of delay defects in deep sub-micron VLSI designs. In this work, we analyze the effect of IR-drop in path-delay test and how to obtain more accurate delay information of critical paths. For possible regions with IR-drop, we perform timing analysis on these nodes such that a certain amount of voltage drop can be associated with extra delays on victim nodes. Power analysis is conducted to determine the occurrence probability of a certain voltage drop. These probability values are used to weigh the extra delays caused by IR-drop of all victim nodes, which are then accumulated along each path. Experimental results show that such a process can effectively take the small delays caused by IR-drop into consideration and can have a significant impact on the identification and analysis of critical paths.