Synchronizers are used to mitigate the effects of metastability in multiple clock domain System-on-Chip devices. In order to enable reliable synchronization, the synchronizer MTBF (Mean Time Between Failures) should be much longer than the product lifetime. To achieve such high margins, multistage synchronizers are used. Several simulation methods have been developed to determine their probability of failure and the number of stages to use. While simulation methods have improved in recent years, accurate analytical models for failure calculations are scant. Some previously published models do not reflect estimations of MTBF but only loose lower bounds that give rise to a high number of synchronizer stages reducing the overall system performance. Others provide improved accuracy but are difficult to operate and simulation for each stage is required. In this paper, we review published analytical models for MTBF calculations of multistage synchronizers. We show that existing models often underestimate MTBF, and in some cases they even overestimate it. A new model that calculates a MTBF lower bound with significantly smaller margins is introduced. These estimates are shown to be consistent with state of the art simulations and measurements. A method for calculating these estimates for a variety of applications is presented based on a limited number of intrinsic synchronizer parameters determined by simulation.