In advanced technology nodes, the BEOL requires advanced patterning techniques such as triple pattering (LELELE) and side wall image transfer techniques to form metal and via structures with pitches below 50nm. This scenario has imposed increased demands on many of the semiconductor processes involved in the fabrication of integrated circuits. One such process is the wet clean process. In this paper, a direct correlation between clean chemistry and metal/via electrical yield is shown in M1 module of 10 nm technology node. Line and via open yield improved 10X upon adding iso propyl alcohol (IPA) to the standard dilute hydrofluoric acid (dHF) aqueous solution. IPA acts as an inhibitor, and reduces the surface tension, thus preventing over-aggressive etch and displacement of pattern structures during the clean process.