Trench etching is an important process step for many semiconductor applications. Memory implementations, power devices and embedded capacitors benefit from lateral shrinkage of trench dimensions. But for physical reasons the depth of a trench that can be achieved for a given diameter is limited. We describe here a process with a sacrificial Silicon-Germanium (SiGe) layer on the sidewall of a trench, that multiplies the number of trenches in a unit cell by five with a correspondent improvement of the aspect ratio, avoiding the difficulties of reactive ion etching.