Cryptographic systems are being compromised by power analysis attacks. In this paper, a novel countermeasure technique against power analysis attacks is proposed which dynamically varies the clock when executing operations (making it difficult to correlate power traces in the time domain) and inserts dummy operations during idling clock cycles (reducing the signal-to-noise ratio of the useful information). Its effectiveness is shown by performing a DPA attack on basic, intermediate (random clock) and advanced (random clock and dummy data) designs for the AES encryption algorithm, implemented on a FPGA-based board. The intermediate design is resistant to classical DPA attacks and the advanced design reduces the SNR by 79% (increasing area by 70% and reducing performance by 5.33%) when compared to the basic design. It is shown that the design is better in both metrics than other countermeasure techniques.