A fully integrated digital modulator/demodulator design for Power Line Communication (PLC) is presented. The proposed design is consisted of Cyclic Redundancy Check (CRC), Pulse Width Modulation (PWM), and Frequency Shift Keying (FSK). The CRC can detect the errors occurred in the digital communication. The function of PWM is to generate the digital pulses that exhibit the same pulse width according to the swing of the input voltage swing. In the telecommunication, FSK is a frequency modulation scheme such that the digital information can be transmitted through the discrete frequency changes of the carrier. The detailed designs of teach block are described. The design is implemented TSMC 0.18µm process. The fabricated chip area is 1.73mm2 with 3.3/1.8 supply voltages. The measured data shows that the proposed design is fully functional and consumes 155µW.