A Switched-Voltage High-Accuracy Sample/Hold Circuit
Kenji Ohno; Hiroki Matsumoto; Kenji Murao;
A Switched-Voltage High-Accuracy Sample/Hold Circuit
In this paper, three switched-voltage (SV) sample/hold (S/H) circuits are presented to compensate for clock-feed-through (CFT) and channel-length modulation effect. They consist of a CMOS SV-delay cell. Thus, the configuration is very simple. The proposed circuits can be operated using simple nonoverlapping two phase clocks. The performance is verified by simulations on PSpice.
- University of Miyazaki Japan
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This is an alternative to the "Influence" indicator, which also reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).
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