This work presents a simple-to-implement, 3D electro-thermal model for circuit-level SPICE simulation of grounded-gate NMOS (ggNMOS), with application for ESD (electrostatic discharge) protection circuit design verification. A new ESD discharging fitting resistor (R/sub on/) is employed to improve ESD electrical modeling in the high-current region and a new 3D thermal resistor parameter (R/sub th/) is proposed to model the electro-thermal characteristics of ggNMOS. The extraction method for the new parameters, R/sub on/ and R/sub th/, is discussed. Finally, simulation results are presented and compared with experimental data.