Dynamic partial reconfiguration (DPR) allows runtime access to the configuration memory (CMEM) of FPGAs. A key function that relies on DPR is task reconfiguration, where circuits are multiplexed in time and space in order to reduce device count and cost. Moreover, in mission-critical applications, DPR is used for soft error mitigation (SEM). These two key functions require access to the same CMEM interface and the recommendation is that more time (> 99%) should be allocated to SEM for continuous full-device reliability. We present a fault-tolerant controller with a fully integrated SEM engine that allows selective-area scanning of the FPGA in order to increase the time available for reconfiguration without compromising reliability. A case study drawn from the NASA JPL's Compositional InfraRed Imaging Spectrometer (CIRIS) instrument shows a time saving of up to 74% over the Xilinx SEM IP when only the data processing core of the CIRIS instrument is considered.