This paper represents a design technique for hardening circuits mapped onto FPGAs. An effective and simple algorithm for signal probabilities has been used to detect SEU (single event upset) sensitive gates for a given circuit. The circuit can be hardened against radiation effects by applying triple modular redundancy (TMR) technique to only these sensitive gates. Selective TMR is tested against different circuits to prove its efficacy. With a small loss of SEU immunity, the proposed scheme can greatly reduce the area overhead as compare to TMR technique. Selective TMR scheme along with the readback and reconfiguration features of FPGAs can result into a very effective SEU mitigation technique.