This paper proposes a Petri-net-based specification of cyber-physical systems dedicated to the control of a direct matrix converter with space vector modulation (SVM) and transistor commutation. The technique employed is further applied for hardware implementation in a programmable logic device [namely, field-programmable gate array (FPGA)]. Contrary to the traditional SVM computation methods, concurrency aspects of the digital devices are highly utilized in the presented solution. Therefore, the hardware system is specified by a live and safe Petri net, which is based on the parallelism. Moreover, such a specification can be easily analyzed and verified against the structural properties in order to avoid formal errors and prototyping mistakes (such as deadlocks or non-reachable states). The proposed idea is illustrated by a case-study example of the real prototype of the SVM algorithm. The system has been specified by a live and safe Petri net, analyzed, verified, and finally implemented in the FPGA device. The obtained results of the physical implementation are presented and discussed.