When thinking of semiconductor memories, it comes naturally to associate stored bits and memory cells with a one-to-one relationship. That, however, is not really a must nor necessarily the most convenient solution for data storage, since using analog signals and digital-to-analog (D/A) as well as analog-to digital (A/D) conversions a large number of bits could be memorized in a single cell, although, of course, the use of analog signals presents all drawbacks of signal-to-noise ratio that are so well known in electronics. In fact, the real question in this sense concerns the number of bits used for the A/D and D/A conversions, since the conventional (fully) digital case can be seen as the simplest realization of a general approach tending to infinitely precise analog storage (i.e. an infinite number of stored bits per cell) at the other extreme. Naturally, in the real world the conflicting aspects of density (measured in bits per cell) and noise immunity (in a general sense) should be traded off one against the other looking for optimum use of silicon area, of course depending on technology, architectures, circuits and reliability. From this point of view it is obvious that the fully digital approach based on the one-bit one-cell concept does not represent necessarily the best solution. Recently, this general question has assumed real and practical significance for nonvolatile memories, since devices storing two bits per cell are now being introduced on the market. At the same time, in a number of research labs a significant effort is currently being dedicated to the study of the limits and practical convenience of storage density considering the current state of the art in technology and circuit designs. This problem, however, presents a number of interacting aspects concerning cell concept, programming and reading schemes, and architectures and reliability that are of interest well beyond the field of nonvolatile memories, because they are ultimately dealing with the basic question of analog versus digital signals. In this contrast, the present paper considers the question of multilevel nonvolatile memories in all its interacting aspects, analyzing both the current state of the art and the future possibilities.