Taking into account RC effects in VLSI simulation and verification systems, without seriously degrading their efficiency, requires preliminary data reduction. A tool, DARSI (data reduction system for interconnects), that can handle both polysilicon and diffusion resistive effects is presented. It contains the reduction scheme described by S.-L. Su et al. (Proc. IEEE Conf. Computer-Aided Design, p.270-3, 1986), a novel line-based reduction method, a novel loop reduction scheme, and a technique for identifying important diffusion resistors. The number of parasitic elements is considerably reduced, while guaranteeing delay errors to be less than a few percent. DARSI is implemented in a general-purpose rule-based verification environment for VLSI and has a nearly linear complexity. Application to several practical designs is also discussed. >