Efficient physical timing models for complex CMOS AND-OR-inverter (AOI) and OR-AND-inverter (OAI) gates have been successfully developed. Through extensive comparisons with SPICE simulation results, the developed models have shown a maximum error of 30% for long-channel and small-geometry CMOS AOI/OAI gates with wide ranges of channel dimensions, capacitive loads, logic input patterns, circuit configurations, device parameter variations, and noncharacteristic waveform input excitations. The error can be further reduced to 16% with the commonly used device dimensions. The developed timing models are successfully applied to the autosizing of CMOS AOI/OAI gates. The results show a good accuracy and a reasonable CPU time consumption. >