Efficient digital techniques for implementing a class of fast phase-locked loops (PLL's)

descriptionPublicationkeyboard_double_arrow_right Article 01 Dec 1996Publisher:Institute of Electrical and Electronics Engineers (IEEE)Journal:IEEE Transactions on Industrial Electronics, volume 43, pages 616-620 (issn: 0278-0046,

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Authors: Fuminori Kobayashi; Masayuki Haratsu; Masateru Yabumoto; Michio Nakano;

doi: 10.1109/41.544548

Efficient digital techniques for implementing a class of fast phase-locked loops (PLL's)

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Abstract

Circuit configurations making use of counters are described to efficiently implement controllers for time-optimal and finite-time responses in phase-locked loops (PLLs). The new PLLs, solving the responsiveness problem with conventional PLLs, require quite complicated operations, including adders and subtracters. The proposed schemes, taking advantage of normal and loadable operations of counters for these operations, provide for gate count savings of about 30%.

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