Realization of Gmicro/200

descriptionPublicationkeyboard_double_arrow_right Article 01 Apr 1988Publisher:Institute of Electrical and Electronics Engineers (IEEE)Journal:IEEE Micro, volume 8, pages 12-21 (issn: 0272-1732,

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Authors: Hideo Inayoshi; Ikuya Kawasaki; Tadahiko Nishimukai; Ken Sakamura;

doi: 10.1109/40.526

Realization of Gmicro/200

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Abstract

The Gmicro/200, a microprocessor that has been developed as part of Japan's TRON (The Real-Time Operating Nucleus) project, is described. This microprogram-based processor with six-state pipeline, 730000 transistors and on-chip caches will serve in an engineering workstation or a high-speed graphics accelerator system. The authors discuss features of the instruction set; memory management; handling of exceptions, interrupts and traps; and the implementation of the Gmicro/200. >

Related Organizations

Hitachi (Japan)
Japan
University of Tokyo
Japan

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