The authors introduce a circuit partitioning method based on analysis of reconvergent fan-out. A corolla is defined as a set of overlapping reconvergent fan-out regions. The authors partition the circuit into a set of disjoint corollas and use the corollas to resynthesize the circuit. The authors develop the notion of resynthesis potential of a logic circuit and use it to select corollas that resynthesize with most gain. It is shown that resynthesis of large benchmark circuits using the corollas consistently reduces transistor pairs and layout area while improving delay and testability. The use of don't cares to further minimize the corollas in the local context and the global context is explored. >