Wide VLSI transistors suffer additional switching delays due to signal propagation when passing through the resistive gate polysilicide. We model and evaluate this resistive effect and define an analytical expression in terms of extra propagation term. This delay can be reduced by breaking up a single wide transistor into smaller transistors connected and driven in parallel. This work develops expressions for deciding how many parallel transistors should be employed so as to limit the additional delay caused by the resistive polysilicide to within desired bounds. The expressions are validated by comparing calculated delay results with those from HSPICE simulations.