The delay of a CML circuit can be described in terms of the delay elements of a bipolar transistor such as junction capacitors C/sub BC/, C/sub BE/, C/sub CS/and a cutoff frequency f/sub T/. A new analysis method is proposed to calculate a CML delay. The nonlinear conductance of a bipolar transistor is approximated by a piecewise linear function. A resistor network is then picked up from the CML equivalent circuit to characterize the dc operation. This resistor network and the delay elements determine the CML delay. Subcircuits containing the resistor network and one or two of the delay elements of C/sub BC/, C/sup BE/, C/sub CS/, and f/sub T/ are separately analyzed to clarify the delay components. The total CML delay is estimated from a linear sum of the delay components for a step input response. Current dependency of the CML delay Is also discussed. >