An analog BiCMOS integrated circuit for front-end RDS decoder

descriptionPublicationkeyboard_double_arrow_right Article , Conference object 01 Jan 1991 Italy Publisher:Institute of Electrical and Electronics Engineers (IEEE)Journal:IEEE Transactions on Consumer Electronics, volume 37, pages 585-591 (issn: 0098-3063,

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Authors: BASCHIROTTO A; CASSIS M; KIRCHLECHNER P; MONTECCHI F; PALMISANO, Giuseppe; ROSSI D.;

doi: 10.1109/30.85571 , 10.1109/icce.1991.733215

handle: 10281/36908 , 10281/36947 , 20.500.11769/46001

An analog BiCMOS integrated circuit for front-end RDS decoder

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Abstract

An analog integrated front-end circuit for the RDS (Radio-Data-System) digital decoder is described. The core of the circuit is an 8th-order switched-capacitor (SC) bandpass filter at 57 kHz with linear-phase response in a 3 kHz bandwidth. A low-offset comparator provides the squared signal for the digital decoder. Antialiasing and smoothing filters are also included in the chip, as well as the clock generation for the SC section; few external components are required. Integrated in a high-performance BiCMOS technology, the circuit operates from a single 5-V supply and dissipates 45 mW. The die size is 5 mm/sup 2/. >

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Italy

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Keywords

5 V; 57 kHz; Radio-Data-System; SC section; analog BiCMOS integrated circuit; analog integrated front-end circuit; antialiasing filters; clock generation; digital decoder; eighth-order switched-capacitor bandpass filter; front-end RDS decoder; linear-phase response; low-offset comparator; smoothing filters; BIMOS integrated circuits; application specific integrated circuits; decoding; linear integrated circuits; radio data systems; radio receivers; switched capacitor filters, RDS

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