The intensive computational demands of vector quantization (VQ) for important applications in speech and image compression and speech recognition have motivated the need for dedicated processors with very high throughput capabilities. Systolic architectures offer one of the most promising approaches for fulfilling the demanding VQ speed requirements in many applications. We propose a novel family of architectural techniques which offer efficient computation of weighted Euclidean distance measures for nearest neighbor codebook searching. The general approach uses a single metric comparator chip in conjunction with a linear array of inner product processor chips. Very high VQ throughput can be achieved for many speech and image processing applications. Several alternative configurations allow reasonable tradeoffs between speed and VLSI chip area required.