The key synchronization aspects in the system design of a QQPSK (quadrature-quadrature phase-shift-keying) modem are addressed. The sensitivity of the data demodulator to synchronization errors is discussed, and contextually the performances of some IF and baseband carrier phase and symbol timing recovery schemes are evaluated both theoretically and by computer simulations. In particular, a fourth-power IF carrier/clock regenerator and two baseband clock recovery schemes, with and without the aid of data decisions, respectively, are taken into account. The analysis shows on the one hand the substantial robustness of QQPSK to carrier phase errors and the adequacy of the examined carrier extraction scheme. On the other hand, the remarkable sensitivity of QQPSK to symbol timing inaccuracy is stressed and the need to resort to the newly proposed decision-aided baseband clock recovery scheme is pointed out. >