Transistors and ICs were irradiated with or without pre-irradiation elevated-temperature biased stresses (i.e., burn-in). These stresses lead to larger radiation-induced transistor threshold-voltage shifts and increases in IC static power supply leakage current (two orders of magnitude) in stressed ICs than for ICs not subjected to a stress. In addition, these stresses led to reduced degradation in timing parameters. The major cause of the differences is less radiation-induced interface-trap buildup for transistors subjected to an elevated-temperature biased stress. These results were observed for two distinctly different technologies and have significant implications on hardness assurance testing. One could significantly (1) overestimate degradation in timing parameters resulting in the rejection of acceptable ICs and increased system cost, or (2) underestimate the increase in static supply leakage current of ICs leading to system failure. These results suggest that radiation qualification testing must be performed on integrated circuits that have been subjected to all high-temperature biased stresses experienced in normal production flow or system use. >