Dynamic clamp for pull-in time reduction

descriptionPublicationkeyboard_double_arrow_right Article 01 Jan 1996Publisher:Institute of Electrical and Electronics Engineers (IEEE)Journal:IEEE Transactions on Instrumentation and Measurement, volume 45, pages 907-909 (issn: 0018-9456,

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Authors: H. Calleja;

doi: 10.1109/19.536709

Dynamic clamp for pull-in time reduction

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Abstract

A dynamic clamp aimed at reducing the pull-in time of a digital phase-locked-loop circuit being fed by intermittent signals is presented. This clamp is useful when the phase-locked loop (PLL) is used as a frequency multiplier, and is based on the assumption that the input signal frequency will not change significantly during the period of disconnection. Details on the additional circuitry required to achieve this goal are given, and experimental results are included.

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