Intercell leakage current characteristics of a stacked trench capacitor cell (STT) are investigated. The primary obstacle in downscaling the trench capacitor is the intercell leakage current caused by the parasitic field MOS transistor. This leakage current, called surface leakage current, is significantly reduced in the STT. This reduction results from the STT structure itself. In the STT, the sidewall of the field oxide between neighboring trenches is covered by the storage node electrode. Therefore, most of the electric field lines, originating at the plate electrode, terminate on the storage node electrode. The influence of the plate bias on the Si surface potential beneath the field oxide is weakened by the storage node electrode. The STT has superior trench-trench isolation characteristics, and it is a promising structure for the 16-Mb DRAM and beyond. >