Junction-isolated CMOS for high-temperature microelectronics

descriptionPublicationkeyboard_double_arrow_right Article 01 Sep 1989Publisher:Institute of Electrical and Electronics Engineers (IEEE)Journal:IEEE Transactions on Electron Devices, volume 36, pages 1,854-1,856 (issn: 0018-9383, eissn: 1557-9646,

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Authors: R.B. Brown; K. Wu; M. Ghezzo; D.M. Brown; E. Downey; D. Hanchar;

doi: 10.1109/16.34256

Junction-isolated CMOS for high-temperature microelectronics

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Abstract

Latchup susceptibility over a temperature range of 25-315 degrees C for variations on a 1.2- mu m CMOS process is studied. A special high-performance process, including all refractory metallization, thinner epi, and higher doping levels, resulted in metal-migration immunity and doubling of the latchup holding voltage and current at 300 degrees C. >

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