A 200-V flat-panel display IC with a novel diffused-well structure

descriptionPublicationkeyboard_double_arrow_right Article 01 Jan 1988Publisher:Institute of Electrical and Electronics Engineers (IEEE)Journal:IEEE Transactions on Electron Devices, volume 35, pages 1,264-1,268 (issn: 0018-9383,

Copyright policy )

Authors: H. Hayama; K. Hirata; H. Sakuma;

doi: 10.1109/16.2546

A 200-V flat-panel display IC with a novel diffused-well structure

- Summary
- Metrics

Abstract

A high-voltage diffused-well structure that allows the low-coast fabrication of a monolithic high-voltage CMOS IC without using any epitaxial layers is discussed. Offset-gate-type PMOSTs for the proposed structure were fabricated within an n-well and a breakdown voltage over 200 V was obtained. A high-performance 200-V CMOS test IC for which high-voltage NMOSTs and low-voltage CMOS peripheral circuits were built in the p-type substrate area was fabricated. Superior latchup immunity was obtained with this structure. A 2200-pF capacitance load corresponding to that of an electroluminescent display panel was successfully driven. >

Related Organizations

NEC (Japan)
Japan

Impact byBIP!

	selected citations These citations are derived from selected sources. This is an alternative to the "Influence" indicator, which also reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).	1
	popularity This indicator reflects the "current" impact/attention (the "hype") of an article in the research community at large, based on the underlying citation network.	Average
	influence This indicator reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).	Top 10%
	impulse This indicator reflects the initial momentum of an article directly after its publication, based on the underlying citation network.	Average