Abstract The SHA-256 algorithm is one of the most widely used secure hashing algorithms. The SHA-256 algorithm is implemented in hardware, and in order to ensure the integrity and authenticity of the encrypted data, this requires higher throughput and efficiency. In this paper, we propose a high-performance hardware architecture for the SHA-256 hash algorithm, which further optimizes the rearranged round computation by decomposing the critical path into two addition stages and replacing the multi-operator adder in the critical path of the algorithmic round-computing circuit with a 4-2 compressor. Based on the experimental results on field-programmable gate arrays, the obtained result shows a significant improvement in the performance of the proposed SHA-256 algorithm when compared with various existing architectures. Its maximum clock frequency is 366 MHz, with a throughput of 1990 Mbps and an improved efficiency of 1.86 Mbps per slice.