The time-interleaved (TI) architecture is an attractive choice when achieving the desired sampling rate is not possible or efficient with a single ADC. Time-interleaved ADCs were first introduced in 1980 by Black and Hodges [1]. In principle, they enable high sampling rates by using multiple ADC channels in parallel. However, the inter-channel mismatches have traditionally limited the performance of this class of converters to low resolutions. Recently, there has been a resurgence of interest in time-interleaved ADCs to push the state of the art in performance, speed, and power consumption. This has been driven by the need for higher sampling rates while facing practical limits and prohibitive costs in process technology. In this chapter, we cover the analysis, performance limitations, and some implementation approaches of time-interleaved ADCs. We augmented the theoretical analysis with an intuitive and practical perspective. However, the analysis is needed to understand the operation of this class of converters and to enable the understanding and development of methods and algorithms to improve their performance.