A background bit‐weight calibration in pipelined successive approximation register ADC is proposed. By exploiting the conversion results of the first stage to determine the injection of the dithered signal and introducing two extra capacitors into the first stage to reduce the range of first‐stage residue, a robust and totally background calibration is implemented. According to the simulation, the signal‐to‐noise and distortion ratio and spurious free dynamic range are improved from 66.3 to 73.3 dB and 78.4 to 85.1 dB, respectively, after calibration.