
doi: 10.1049/el.2016.3368
handle: 1854/LU-8200310
An improved bang‐bang phase detector (PD) for multi Gb/s clock and data recovery (CDR) circuits is presented. The proposed PD is based on inverting the Alexander PD. In a typical subsampled CDR circuit, this Inverse Alexander PD results in a ten times better bit error rate (BER) compared with the conventional Alexander PD. Additionally, in the case of duty‐cycle distorted input data, this Inverse Alexander PD can even reach 20 times better BER compared with the conventional Alexander PD.
Technology and Engineering, BER, CLOCK, duty-cycle distorted input data, RECOVERY, inverse Alexander phase detector, bit error rate, inverse Alexander PD, improved bang-bang phase detector, phase detectors, IBCN, clock and data recovery circuits, subsampled CDR circuit, error statistics
Technology and Engineering, BER, CLOCK, duty-cycle distorted input data, RECOVERY, inverse Alexander phase detector, bit error rate, inverse Alexander PD, improved bang-bang phase detector, phase detectors, IBCN, clock and data recovery circuits, subsampled CDR circuit, error statistics
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