
doi: 10.1049/el.2009.3637
handle: 10553/49660
Satisfiability problems (SAT) for register transfer level designs combine arithmetic blocks with Boolean logic to form a mixed integer linear programming (MILP) environment. The classic model of the two-input n-bit adder for MILP is straightforward. However, proposed is a more efficient method using a new set of inequalities that describes its integer hull polyhedron. This special model reduces the number of branches needed to solve the whole integer problem, optimising the overall efficiency of the SAT solver. Experimental results show a CPU time reduction greater than one order of magnitude or higher, depending on the size of the problem.
0,665
0,97
SCIE
349
348
Q1
Q3
computability, adders, Linear programming, 3307 Tecnología electrónica, digital arithmetic, Boolean algebra, integer programming
computability, adders, Linear programming, 3307 Tecnología electrónica, digital arithmetic, Boolean algebra, integer programming
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