A novel mixed analogue/digital design of a phase picking algorithm in an oversampling clock phase recovery is presented. The proposed approach results in reduced processing time, improved integrability with analogue front-end and low noise generation. Simulations of a 10 Gbit/s burst-mode clock phase alignment circuit in a 0.25 μm SiGe BiCMOS process, show a simulated processing delay of only 280 ps.