AbstractIn the era of internet and computer networking the need for security have increased rapidly. Various crypto algorithms are used for secured data transmission and reception through the network, of which hash function possess a key role in various cryptographic protocols. Keccak algorithm is the winner of SHA-3 competition conducted by NIST. SHA-3 consists of different variant such as 224, 256, 384 and 512 bit. This paper discuss the design and implementation of SHA-3 256- bit core. The core is designed using Verilog HDL and prototyped using Xilinx® Virtex®-6FPGA.