Abstract Though bias-stress instability in organic thin film transistors (OTFTs) has been studied in a variety of architectures, it is as yet poorly understood. We have investigated the bias-stress effect in fully solution-processed TIPS-pentacene based OTFTs with polymer dielectric by applying prolonged gate-source voltage (V GS ). The interface is deliberately defect engineered to obtain excellent adhesion and reasonably good steady state characteristics. Both increasing and decreasing behavior of drain-source current (I DS ) drift over 3000s have been observed, and analyzed in terms of electron capture and emission respectively. The step-by-step change in V GS is compared with the one step change from V GS = 0V to V GS = −40V. It has been observed that, for the case of step-wise increase in gate bias, the I DS transients are slower by many orders of magnitude than if the V GS is directly switched to deep bias (−40V) in a single step. A phenomenological model is used to explain the I DS decaying transients. The field induced emission of carriers from interfacial traps is shown to be central to the model and experimental features. The effect due to a prolonged application of drain-source voltage (V DS ) is small, though noticeable in terms of increasing the I DS only by 3% with continuous application of V DS for 3000 s.