Abstract In this paper, the total ionizing dose (TID) response of Ultra-Thin SOI (UTSOI) transistor is presented. TID experiments were performed on both NMOS and PMOS transistors under three different bias configurations (ON-state, OFF-state, TG-state). The results show that the OFF bias is relatively worse compared to other bias configurations for both NMOS and PMOS transistors. And the TID response variability caused by bias configuration during irradiation is small in UTSOI transistors. Besides this, the impact of back gate bias on TID response is also investigated. When a positive back bias is applied on NMOS transistor to achieve better performance, the threshold voltage degradation caused by TID becomes worse. While the negative back bias of PMOS transistor can lead to both better performance and higher TID tolerance. An explanation of back gate impact on front gate TID response is given with TCAD simulation.