Abstract Increased demands for the integration density of electronics initiate a turnaround in packaging technologies, away from packaged constructions towards bare-chip-assemblies. A particular challenge of using bare-chips is the avoidance of chip fracture during processing and subsequent use. In this study a comprehensive portfolio of methods to predict the risk of chip fracture for bare-chips is shown. The basis is an investigation on the influences of different dicing techniques on the breaking strength of silicon chips. The stress resistivity of the chips shows huge differences, for instance 110 MPa after diamond-scribing up to 1473 MPa after thermal-laser-separation. Additionally, damages induced by the dicing were studied using scanning electron microscopy. The analysis of the size effect of diced silicon chips enabled to calculate the scaling parameter which is a size and stress independent strength value. All obtained results were used to develop a probabilistic reliability model for bare-chip-assemblies which describes the risk of chip fracture during the die attachment.