Abstract A simple experimental technique aimed at the spatial localization of the dominant trap states involved in drain current dispersion in GaN HEMTs will be presented. By analyzing the dependence of current dispersion from the gate voltage base-line ( V Gbl ) used in double pulse I – V measurements it is possible to observe a different trend of said dispersion when caused by buffer or barrier/surface traps. Devices whose dynamic characteristics are mainly affected by buffer traps are showing the largest dispersion when V Gbl approaches the device threshold voltage ( V TH ) while a reduction in dispersion is observed when V Gbl is lowered below V TH . On the other hand, when dynamic characteristics are mainly affected by barrier/surface traps, the opposite trend is observed, i.e. dispersion increases when V Gbl is lowered below V TH . Numerical simulations supporting the proposed measurement technique and traps characterization in Fe-doped buffer devices will also be presented.