Wafer-level Cu–Cu bonding technology

descriptionPublicationkeyboard_double_arrow_right Article 01 Feb 2012 English Publisher:Elsevier BVJournal:Microelectronics Reliability, volume 52, pages 312-320 (issn: 0026-2714,

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Authors: Ya-Sheng Tang; Yao-Jen Chang; Kuan-Neng Chen;

doi: 10.1016/j.microrel.2011.04.016

Wafer-level Cu–Cu bonding technology

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Abstract

Semiconductor industry currently utilizes copper wafer bonding as one of key technologies for 3D integration. This review paper describes both science and technology of copper wafer bonding with regard to present applications. The classification of Cu bonding, bonding mechanisms, process developments, its microstructure evolution, as well as other characterizations are reviewed. Researches about patterned Cu bonding, future prospects, and 3D integration using Cu bonding are discussed in this paper.

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National Chiao Tung University
Taiwan

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