Modeling the dynamic behavior for resistive shorts and opens at switch-level dictates the characterization of enhanced delay due to these faults with respect to the input combinations, fault sites, defect resistance and technology variation. The resistive fault model is applied to CMOS technologies with feature sizes of 350 nm, 180 nm, 90 nm, 45 nm and 32 nm, respectively. This model is targeted to transistor-level CMOS circuits. A static defect in a circuit (shorts or opens) is replaced by a resistor and a simple electrical analysis of the circuit is performed to obtain the timing variations which occurred during propagation of a logic value from gate inputs to gate output.