Abstract This paper investigates the effect of NFET (N+ poly gate, N+ diffusion of FET) stress voltage conditions, for ultra-thin gate oxides, on the voltage acceleration, and lifetime projections to use conditions. This work employs the model relating the critical defect density (NBD) to the charge-to-breakdown and the defect generation probability (Pg). The models for NBD and Pg were adjusted for effects at voltages between 2 V and 3 V, and oxide thickness less than 2.7 nm. For NBD, a model is proposed that is supported by published data and provides a gradual transition to a plateau for oxide thickness less than 2.7 nm. For Pg, a stronger dependency of Log(Pg) in the range of 2–3 V is employed to give a better fit to published data. This adjusted Pg is also used below 2 V to show trend of projection. In the direct tunneling range below 3 V, there is an increase of the voltage acceleration factor (AF) with decreasing voltage. Also, below 3 V, AF shows a decrease as the oxide thickness is reduced from 2.0 nm to 1.2 nm, and this trend becomes stronger as the gate voltage is reduced. Above a gate stress voltage of 3 V, in the range of 3–4 V, AF is almost constant, and there is a slight decrease of AF with decreasing oxide thickness in the range of 2.0–1.2 nm. A voltage power-law fit for the range above 3 V shows a decreasing power index with decreasing oxide thickness.