
arXiv: 2012.02037
In this work, we consider error detection via simulation for reversible circuit architectures. We rigorously prove that reversibility augments the performance of this simple error detection protocol to a considerable degree. A single randomly generated input is guaranteed to unveil a single error with a probability that only depends on the size of the error, not the size of the circuit itself. Empirical studies confirm that this behavior typically extends to multiple errors as well. In conclusion, reversible circuits offer characteristics that reduce masking effects -- a desirable feature that is in stark contrast to irreversible circuit architectures.
6 pages, 9 figures
Error detection, FOS: Computer and information sciences, Computer engineering. Computer hardware, Computer Science - Emerging Technologies, QA75.5-76.95, Quantum computing, TK7885-7895, Emerging Technologies (cs.ET), Emerging technologies, Electronic computers. Computer science, Hardware Architecture (cs.AR), Reversible logic, Computer Science - Hardware Architecture, Simulation
Error detection, FOS: Computer and information sciences, Computer engineering. Computer hardware, Computer Science - Emerging Technologies, QA75.5-76.95, Quantum computing, TK7885-7895, Emerging Technologies (cs.ET), Emerging technologies, Electronic computers. Computer science, Hardware Architecture (cs.AR), Reversible logic, Computer Science - Hardware Architecture, Simulation
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