Publisher Summary This chapter addresses the application of silicon-on-insulator (SOI) structures to very large-scale integrated (VLSI) circuits based on micro-structures whose dimensions are in the neighborhood of one micron and less. This class of integrated circuits also includes those circuits planned in the very high-speed integrated circuit (VHSIC) program. The chapter also discusses the various considerations and motivation for the application of the SOI structure to VLSI and VHSI circuits, and describes the more promising new approaches to the realization of an SOI technology for VLSI and VHSI. The two basic SOI structures differ primarily in the substrate type. The most desirable or ideal structure consists of defect-free single-crystal silicon on the insulating substrate or film. In addition, the desired silicon-insulator interface is one possessing minimum mechanical stress and minimum electrical surface states, and allowing the realization of defect-free single-crystal silicon throughout the silicon film up to the silicon-insulator interface. The trends in silicon MOS integrated circuits are well-known: greater complexity, higher speed, lower power per function, greater functional versatility, and improved reliability. This trend has been supported primarily by the parallel trend of rapidly decreasing feature size in the circuits. The trend of increasing device and circuit densities must and will persist to allow the cost per function to continue to decrease, to provide more capability per chip, and to improve performance.