Symbolic trajectory evaluation for word-level verification: theory and implementation
Copyright policy )Symbolic trajectory evaluation for word-level verification: theory and implementation
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- Indian Institute of Technology Bombay India
- Intel (Israel) Israel
- Indian Institue of Technology, Bombay India
- Intel (United States) United States
- Chalmers University of Technology Sweden
symbolic trajectory evaluation, SMT solving, invalid-bit encoding, Specification and verification (program logics, model checking, etc.), Rtl Verification, hardware verification, Symbolic Simulation, 005, symbolic simulation, Invalid-Bit Encoding, Smt Solving, X-based abstraction, Hardware Verification, RTL verification, Word-Level Verification, word-level verification, X-Based Abstraction, Symbolic Trajectory Evaluation
symbolic trajectory evaluation, SMT solving, invalid-bit encoding, Specification and verification (program logics, model checking, etc.), Rtl Verification, hardware verification, Symbolic Simulation, 005, symbolic simulation, Invalid-Bit Encoding, Smt Solving, X-based abstraction, Hardware Verification, RTL verification, Word-Level Verification, word-level verification, X-Based Abstraction, Symbolic Trajectory Evaluation
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