Effect of multicycle instructions on the integer performance of the dynamically trace scheduled VLIW architecture

descriptionPublicationkeyboard_double_arrow_right Part of book or chapter of book , Conference object , Article 01 Jan 1999Publisher:Springer Berlin Heidelberg

Authors: Alberto Ferreira de Souza; Peter Rounce;

doi: 10.1007/bfb0100690

Effect of multicycle instructions on the integer performance of the dynamically trace scheduled VLIW architecture

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Abstract

Dynamically trace scheduled VLIW (DTSVLIW) architectures can be used to implement machines that execute code of current RISC or CISC instruction set architectures in a VLIW fashion, delivering instruction level parallelism (ILP) with backward code compatibility. This paper presents the effect of multicycle instructions on the performance of a DTSVLIW architecture running the SPECint95 benchmarks.

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University College London
United Kingdom

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