Formal specification and verification of VHDL

descriptionPublicationkeyboard_double_arrow_right Part of book or chapter of book , Conference object , Article 01 Jan 1996Publisher:Springer Berlin Heidelberg

Authors: Mark Bickford; Damir Jamsek;

doi: 10.1007/bfb0031818

Formal specification and verification of VHDL

- Summary
- Metrics

Abstract

We give an overview of our system for the verification of VHDL designs1, and discuss its rationale. We present a complete example of a simple processor and discuss general methods for specification of state machines and timed and untimed combinational circuits.

Impact byBIP!

	selected citations These citations are derived from selected sources. This is an alternative to the "Influence" indicator, which also reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).	4
	popularity This indicator reflects the "current" impact/attention (the "hype") of an article in the research community at large, based on the underlying citation network.	Average
	influence This indicator reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).	Top 10%
	impulse This indicator reflects the initial momentum of an article directly after its publication, based on the underlying citation network.	Average