In this paper we consider the relationship between algorithms and parallel VLSI architectures. Starting from the premise that VLSI is the natural habitat for parallel algorithmics, we outline the desirable features of VLSI architectures. Next we discuss the notion of algorithmic paradigm, as the data transfer pattern of a class of specific algorithms. The recursive combination paradigm (applicable to merging, sorting, FFT, permutation, etc.), is naturally mapped to the awkward binary cube architecture. Thus we analyze four viable architectures — the shuffle-exchange, the linear array, the mesh, and the cube-connected-cycles — which emulate the binary cube. Finally, we illustrate the mechanisms of pipelining, pleating, and mixing, which play a significant role in matching algorithms and architectures.