This paper describes a processor design and gives its estimated performance through trace-driven simulation. The processor runs four threads in parallel and issues up to four instructions per thread per cycle. In order execution is assumed to keep the pipeline stages simple enough to have a very short cycle width. Moreover, all the arithmetic operators -adders, incrementers, shifters, multiplier and dividerhave been sliced and pipelined with no execute stage including more than the equivalent of a 16 bits adder in its critical path. The first simulation results show a sustained rate of 5 instructions per cycle.