Hazard simulation of sequential circuits

descriptionPublicationkeyboard_double_arrow_right Article 01 Apr 1996 English Publisher:Springer Science and Business Media LLCJournal:Journal of Electronic Testing: Theory and Applications (JETTA), volume 8, pages 215-217 (issn: 0923-8174, eissn: 1573-0727,

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Authors: Kanji Hirabayashi;

doi: 10.1007/bf02341825

Hazard simulation of sequential circuits

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Abstract

A 7-valued logic appropriate for hazard simulation of sequential circuits is investigated in this letter. The 5-valued system of Lin and Reddy is extended to discriminate transitions with and without hazard. We assume that hazards are damped in the feed-back loop of flip-flops, and introduce a kind of filter to assure it. The application to hazard checking is demonstrated for counter circuits.

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Toshiba (Japan)
Japan
Akita Industrial Technology Center
Japan

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